This invention relates generally to logic level translators and more particularly, it relates to a translator circuit for converting complementary metaloxide semiconductor (CMOS) logic level signals to emitter-coupled-logic (ECL) logic level signals which have a higher speed of operation than is traditionally available.
As is generally well known in the art, various types of digital logic circuitry are widely utilized in the area of computer data processing systems in different parts of the processing system. In order to transfer data from one part of the processing system having one logic type (i.e., CMOS) of integrated circuit devices to another part having another logic type (i.e., ECL) of integrated circuit devices, there is often required a translation from one logic type to the other logic type since they have different switching speeds and the input/output voltages corresponding to high and low logic levels are different. Since many of these processing systems are designed with both CMOS and ECL logic circuits, there are required interface circuits such as CMOS-to-ECL translators so that these two different types of logic circuits will be compatible with each other. In other words, the CMOS-to-ECL translators are used to shift the level of the CMOS input logic signals to a level which will be recognized by the ECL logic circuits.
A CMOS-to-ECL logic level translator 2 of the prior art is shown in FIG. 1 and has been labeled "Prior Art." With the advent of advanced process technologies, the N-type MOS transistors N3, N4 and the bipolar transistors Q1, Q2 used in the circuit of FIG. 1 may now be prepared on a single semiconductor chip through a known CMOS fabrication process. In particular, each of the NPN-type bipolar transistors Q1 and Q2 is made as a vertical transistor by utilizing the n region (source or drain) of the N-type MOS transistor as an emitter, the p-well region as the base and the n substrate as a collector.
The logic level translator 2 can convert the CMOS complementary input signals D and DB applied to respective input terminals 4, 6 (gates of the MOS transistors N4, N3) into ECL differential output signals Q and QB at the respective output terminals 8, 10. However, if the switching speed is required to be extremely fast (i.e., in the order of one or two nanoseconds), the bipolar transistors Q1, Q2 will not be able to switch fast enough since the CMOS fabrication process has not been optimized to produce high speed bipolar transistors. Thus, the prior art translator 2 has the disadvantage of being slow. Since speed is a primary advantage of bipolar transistor devices, the slowness of the prior art translator is a serious problem.
Accordingly, there has arisen a need in the industry to provide a logic level translator circuit which has a high speed of operation and is compatible in a CMOS-ECL integrated circuit. The logic level translator circuit of the present invention is an improvement over the prior art translator of FIG. 1. The present translator circuit has a propagation delay during a low-to-high or high-to-low output transition at its output terminal which is reduced to approximately 1-2 ns over the translator of FIG. 1.